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Abstract.
The article is devoted to the design problem of a self-timed multiplier with accumulation in accordance with the IEEE 754 standard. The article analyzes and compares two manual design cases of a multiply-accumulate block. In the first case, multiplication and subsequent addition and subtraction of operands are performed in a ternary self-timed code. The second case uses dual-rail coding of operands and operation results for these purposes. The final stages of the operation result normalization and rounding in both cases use dual-rail coding for all data. The article shows that the hardware costs of the dual-rail multiplier case in the complementary metal-oxide-semiconductor (CMOS) technology basis are 16% less than the ternary case complexity due to easier one-bit adder implementation in 2.8 times, despite the fact that total summation stages in its Wallace tree equals to 7 instead of 4 in the ternary multiplier case. As a result, the ternary multiplier case's layout implementation, when manufactured in 65-nm CMOS process, takes up 26% more chip area than the case with a dual-rail multiplier. This causes the performance of the ternary multiplier case, taking into account the parasitic parameters extracted from the layout, is 11% worse than the dual-rail case.
Keywords:
self-timed circuit, multiplier with accumulation, dual-rail code, ternary code, ECAD, cell library.
DOI 10.14357/20718632260111
EDN TMIEDQ
PP. 122-132.
References
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